Low temperature growth and reliability of ferroelectric memory cell integrated on Si with conducting barrier stack

Journal Article

Dhote, A.M, S Madhukar, D Young, T Venkatesan, Ramamoorthy Ramesh, C.M Cotell, J.M Benedetto

10.1557/JMR.1997.0218

Polycrystalline LSCO/PNZT/LSCO ferroelectric capacitor heterostructures were grown by pulsed laser deposition using a composite conducting barrier layer of Pt/TiN on poly-Si/Si substrate. The growth of the ferroelectric heterostructure is accomplished at a temperature in the range of 500-600°C. This integration results in a 3-dimensional stacked capacitor-transistor geometry which is important for high density nonvolatile memory (HDNVM) applications. Transmission electron microscopy shows smooth substrate-film and film-film interfaces without any perceptible interdiffusion. The ferroelectric properties and reliability of these integrated capacitors were studied extensively at room temperature and 100°C for different growth temperatures. The capacitors exhibit excellent reliability, both at room temperature and at elevated temperatures, making them very desirable for HDNVM applications.

Journal of Materials Research

12

1997

08842914

cited By 6

No Organization

Ramesh Lab