Low temperature growth and reliability of ferroelectric memory cell integrated on Si with conducting barrier stack

Publication Type:

Journal Article

Authors:

A.M. Dhote; S. Madhukar; D. Young; T. Venkatesan; Ramamoorthy Ramesh; C.M. Cotell; J.M. Benedetto

Source:

Journal of Materials Research, Materials Research Society, Volume 12, Number 6, p.1589-1594 (1997)

Keywords:

Capacitors, Conducting barrier stacks, crystal growth, deposition, Ferroelectric capacitors, Ferroelectric materials, ferroelectricity, Heterojunctions, High density nonvolatile memory (HDNVM), Interfaces (materials), Low temperature growth, Low temperature phenomena, Nonvolatile storage, pulsed laser deposition, reliability, Semiconducting silicon, transmission electron microscopy

Abstract:

Polycrystalline LSCO/PNZT/LSCO ferroelectric capacitor heterostructures were grown by pulsed laser deposition using a composite conducting barrier layer of Pt/TiN on poly-Si/Si substrate. The growth of the ferroelectric heterostructure is accomplished at a temperature in the range of 500-600°C. This integration results in a 3-dimensional stacked capacitor-transistor geometry which is important for high density nonvolatile memory (HDNVM) applications. Transmission electron microscopy shows smooth substrate-film and film-film interfaces without any perceptible interdiffusion. The ferroelectric properties and reliability of these integrated capacitors were studied extensively at room temperature and 100°C for different growth temperatures. The capacitors exhibit excellent reliability, both at room temperature and at elevated temperatures, making them very desirable for HDNVM applications.

Notes:

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